Senior Timing Engineer

About the Role

We are seeking a Senior Timing Engineer based in County Cork, Ireland, to lead the development, optimization, and validation of timing methodologies focused on standard-cell library characterization, timing models, variation-aware timing, and timing sign-off processes. This position offers a relocation package.

Key Responsibilities

• Create and improve timing-related methodologies including standard-cell libraries, Low Voltage Falloff (LVF), and variation-aware timing models.
• Develop and enhance library characterization processes and flows.
• Analyze and correlate outputs from different timing sign-off tools with SPICE simulations.
• Assess timing metrics such as noise, Monte Carlo simulations, process, voltage, and temperature variations.
• Automate engineering flows utilizing scripting languages such as Python, Perl, TCL, and Bash.
• Collaborate on SPICE extraction, modeling, aging, and reliability models for cutting-edge semiconductor technology nodes.
• Support and refine Static Timing Analysis (STA) and timing sign-off methodologies.
• Work closely with physical design teams covering synthesis, placement, routing, and timing closure activities.

Candidate Profile

• Proven experience in semiconductor timing methodologies and timing sign-off verification.
• Expertise in standard-cell library characterization and timing model development.
• In-depth knowledge of variation-aware timing methodologies including LVF, AOCV, POCV, and SOCV.
• Experience in correlating timing sign-off tools with SPICE simulations.
• Strong understanding of timing, noise, Monte Carlo, and process variation analyses.
• Familiarity with EDA and CAD tools used in ASIC timing and physical design workflows.
• Proficient in scripting and automation using Python, Perl, TCL, and/or Bash.
• Working knowledge of SPICE extraction, modeling, and aging/reliability analyses.
• Understanding of advanced semiconductor technology nodes and modern physical design methodologies.
• Expertise with STA and timing sign-off procedures.

Preferred Qualifications

• Master's degree in Electrical, Electronic, Computer Engineering, Computer Science, or related field.
• At least 3 years of relevant ASIC, semiconductor design, verification, validation, integration, or timing experience.
• Minimum 2 years' experience working with architecture, ASIC, or EDA design tools.
• Over 2 years' experience in scripting or programming languages.
• Experience in design verification and semiconductor implementation methodologies.