IC Layout Engineer

Role Overview

In this position, the engineer will be responsible for creating precise and high-quality layouts spanning Standard Cells, I/O pads, and Mixed-Signal IP using advanced semiconductor processes, adhering to project deadlines.

Primary Responsibilities

• Execute layout designs by following established design rules and process guidelines to ensure reliable and high-performance outcomes.
• Independently handle planning and floorplanning tasks from the transistor level through cell and block levels, managing project schedules effectively.
• Quickly integrate new layout methodologies, share innovative ideas, and maintain effective communication with engineering teams across multiple locations.

Qualifications and Skills

• Bachelor's degree in Electronic Engineering with 3 to 4+ years of practical experience in IC layout.
• Expertise in layouts involving Standard Cell, Memory, Full Custom, and Analog/Mixed-Signal circuits.
• Comprehensive knowledge of ESD and Latch-up protection mechanisms for I/O design.
• Strong understanding of technologies at deep sub-micron and advanced nodes such as 5nm, 3nm, 2nm, and 1.4nm.
• Proficient use of Cadence Virtuoso for layout design and Calibre tools for physical verification including DRC, LVS, ERC, antenna checks, and EM/IR analysis.
• Experience with scripting languages such as Shell, Python, Tcl, or programming in Cadence SKILL is advantageous.
• Self-driven with the ability to work independently and contribute effectively as part of a collaborative team.