Senior IC Layout Engineer

About the Role

Anradus Pte Ltd is seeking an experienced Senior IC Layout Engineer to join their semiconductor team based in Ang Mo Kio, Singapore. This is a full-time, permanent position requiring work from Monday to Friday, 9:00 AM to 6:00 PM. The compensation package includes a basic salary, meal allowance, variable bonus, and medical and dental benefits.

Main Responsibilities

• Translate schematic diagrams into detailed layout designs defining the physical IC structure.
• Carry out floor planning and device placement strategically to optimize design functionality.
• Handle routing of power and signal lines while enhancing signal and power integrity.
• Execute various physical verification checks such as DRC, LVS, ERC, ANT, ESD, PERC, and LVL to ensure design compliance.
• Ensure designs satisfy all DRC and LVS criteria for manufacturability.
• Prepare comprehensive layout documentation and participate actively in layout review sessions.
• Adhere to established checklists and techniques to guarantee high-quality layouts.
• Continuously refine layout methodologies to improve efficiency and output quality.
• Engage in post-layout tuning and coordination related to blocks or IP cores.
• Apply foundational knowledge in Analog Mixed-Signal (AMS) layout concepts including EMIR, RC delay, decoupling capacitor design, and latch-up prevention measures.
• Provide mentorship and technical guidance to junior layout engineers to develop their skills.
• Contribute to the formulation and advancement of layout best practices and methodologies within the organization.
• Perform other related duties as assigned by management.

Required Qualifications and Experience

• A diploma or bachelor's degree in Electrical Engineering, Computer Engineering, Electronics Engineering, or an equivalent field.
• Minimum of six years of practical experience in IC layout engineering.
• Proven expertise working with technology nodes smaller than 16nm, including experience in high-speed or RF layouts and proficiency with FinFET technology.
• Competency in Cadence SKILL or comparable programming tools for PCell development, with knowledge of scripting languages such as Perl, Python, or TCL for automating layout processes.
• Strong comprehension of semiconductor process technologies, circuit design principles, and analog layout physical verification CAD setup.
• Experience with TX/RX, PLL, ADC/DAC circuits, and analog/digital chip-top integration is considered advantageous.
• Demonstrated capability in overseeing layout quality and providing technical direction to team members.

Additional Information

• Work schedule: Monday to Friday, 9 AM to 6 PM (5 working days).
• Location: Ang Mo Kio, Singapore.
• Permanent employment contract with comprehensive salary and benefits package.

Application Process

Please submit your application through the provided channel stating reference #10248. The review process is efficient, typically completed within three working days. If you do not receive feedback in this timeframe, kindly consider your application not shortlisted and continue your job search.