Principal AMS Layout Engineer

Overview

Join Synopsys, a global pioneer in semiconductor design and verification, to drive innovations that influence the era of pervasive intelligence. This role focuses on high-speed analog and mixed-signal layout engineering, particularly involving multi-Gbps NRZ and PAM-based SerDes across advanced CMOS, FinFET, and GAA technology nodes. The position offers an opportunity to lead methodology development, collaborate across teams, and mentor engineering talent within an innovative and fast-paced environment.

Key Responsibilities

• Define and oversee layout project scope, schedules, resource allocation, and deliverables, including customer-specific requirements.
• Accelerate design development for high-speed SerDes IP, ensuring top quality, timeliness, and budget adherence.
• Serve as the chief technical liaison with clients and internal stakeholders, communicating status, risks, and mitigation plans effectively.
• Interpret customer needs into detailed technical specifications and refine workflow processes accordingly.
• Conduct root-cause analysis and hands-on debugging to resolve complex layout challenges.
• Collaborate on layout solutions considering advanced packaging technologies such as 2.5D/3D packaging, interposers, and bump strategies.
• Develop and enhance end-to-end layout workflows to boost quality consistency and development efficiency.
• Innovate analog and mixed-signal layout methods utilizing industry-standard and proprietary automation tools.
• Ensure design signoff quality encompassing DRC/LVS, EM/IR analysis, reliability, parasitic effects, and tapeout readiness.
• Produce and maintain comprehensive technical documentation, guidelines, and deliverables intended for internal and customer use.
• Mentor junior engineers and promote best practices through sharing knowledge and fostering teamwork.

Impact of the Role

• Enhance the quality and competitiveness of next-generation high-speed SerDes IP targeting advanced technology nodes.
• Drive process innovation that improves efficiency and first-pass success across multiple global product portfolios.
• Transform complex customer requirements into executable engineering strategies, influencing client experience positively.
• Shape future directions in layout methodology, automation, and advanced-node practices.
• Elevate team skills via mentorship and encourage a continuous improvement culture.
• Enable dependable program delivery that advances customer product success and accelerates time-to-market.

Required Skills and Expertise

• Extensive experience with high-speed SerDes layout and analog/mixed-signal circuit design.
• Strong background in multi-Gbps NRZ and PAM4 SerDes architectures is preferred.
• Proficiency in high-speed and signal-integrity layout techniques including differential routing, shielding, clock/data path optimization, and inductor coil design.
• Familiarity with ESD design constraints, latch-up prevention, and custom digital logic cell layout and path routing.
• Expertise in reliability-focused layout elements like electromigration (EM), IR drop, self-heating, and parasitic-aware techniques such as matching, symmetry, and proximity mitigation.
• Experience porting layouts across different nodes and semiconductor foundries.
• Strong debugging capabilities with emphasis on root cause identification in layout issues.
• Hands-on experience with Synopsys Custom Compiler or equivalent custom layout tools.
• Familiarity with layout verification tools including ICV, Star-RCXT, PERC, or their counterparts.
• Knowledge of project management tools such as Jira or other Atlassian products.
• Understanding of advanced packaging technologies including 2.5D/3D ICs, interposers, and bump strategies is beneficial.

Personality Traits and Work Style

• Proactive and inventive problem solver with a collaborative mindset.
• Strategic thinker balancing deep technical expertise with a broader product vision.
• Clear and effective communicator able to explain complex information across diverse groups.
• Dedicated mentor supporting team development and knowledge growth.
• Resilient and adaptable leader capable of handling multiple fast-moving projects simultaneously.

Team Environment

The successful candidate will join the High-Speed Mixed-Signal IP Layout Team, a group specializing in full-custom analog and ASIC layout solutions for high-performance integrated circuits. The team fosters a collaborative culture, modern tooling, and a commitment to innovative engineering practices. As a Principal Engineer, you will partner closely with layout engineers, circuit designers, and CAD experts to shape best-in-class methodologies and deliver world-class products to a global customer base.

Compensation and Benefits

Synopsys provides a robust benefits package covering health, wellness, and financial support for employees and their families. Details regarding salary and benefits will be shared during the recruitment process.