Chip Physical Verification Data Engineer (Mid/Senior)

Job Overview

This role focuses on managing the extraction, transformation, and loading (ETL) of data produced throughout various stages of the IC design cycle, specifically during the physical verification phase. Candidates will be responsible for integrating data sourced from multiple EDA software tools such as Calibre, DRV, ICV, Fusion Compiler, and Innovus, along with design databases including netlists and layout files, as well as workflow management systems.

Key Duties

• Engineer and enhance data workflows to streamline collection and support analytical processing, machine learning initiatives, and dashboard reporting.
• Maintain high standards of data integrity, governance, and security across all data operations.
• Supervise the performance of data jobs, setting up automation and alerts as needed to ensure system reliability.
• Operate on an on-premises data platform.
• Partner with data analysts and business units to clarify needs and assure data quality and accessibility.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering or Computer Science.
• Strong command of EDA tools such as Calibre, DRV, Laker, and ICV, combined with a solid understanding of IC design workflows for effective design data extraction.
• Proficient programming experience in Python or Perl and expertise with MongoDB for data manipulation.
• Excellent analytical skills, with the ability to verify data accuracy and solve related problems efficiently.
• Effective communication and teamwork skills to thrive in a fast-moving, collaborative environment.
• Knowledge of database management systems like MySQL and graph databases (Neo4j) is advantageous.
• Work location: One North, Singapore.