Physical Verification Sign-off Engineer

Job Overview

The role involves overseeing the comprehensive physical verification sign-off process for full-chip layouts, focusing on areas such as Design Rule Check (DRC), Layout Versus Schematic (LVS), Antenna checks (ANT), Electrical Rule Check (ERC), Electrostatic Discharge (ESD), and Parasitic Extraction Rule Check (PERC) to ensure readiness for tape-out.

Main Responsibilities

• Collaborate with the Place & Route team to address and resolve issues related to full-chip layout integration.
• Coordinate with internal IP owners to manage and resolve any IP-related concerns.
• Work with the Manufacturing Team to tackle DRC-related problems effectively.
• Develop and implement automation solutions aimed at enhancing efficiency throughout the tape-out workflow.
• Provide detailed reporting on tape-out issues to relevant stakeholders.

Qualifications and Skills

• Possession of a Bachelor's or Master's degree in Electrical/Electronics Engineering or Computer Science.
• Practical knowledge of integrated circuit (IC) design processes from front-end to back-end.
• Preferable familiarity with industry tools including Calibre, Assura, and Star-RCXT.
• Strong scripting abilities, especially in languages like Tcl, Perl, or C-shell.
• Experience working with UNIX or Linux operating systems.
• Excellent communication, analytical thinking, and problem-solving capabilities.