Senior IP Design Verification Engineer - Memory Subsystems

About the Role

We are looking for a highly skilled Senior Verification Engineer to lead the validation of next-generation memory subsystem designs used in advanced GPUs and System on Chips (SoCs). This role offers the chance to contribute significantly within a cutting-edge technology firm influencing product lines from consumer graphics to AI-driven autonomous vehicles. Joining a globally distributed team of exceptional professionals, you will help push the technological boundaries that shape the future of computing.

Our GPUs have evolved from powering visual imagination in gaming and film to simulating human intelligence. Today, they serve as computing brains for robots, self-driving cars, and AI applications, positioning us as a pioneering AI computing company.

Key Responsibilities

• Conduct comprehensive verification of ASIC design, architecture, and micro-architecture for memory subsystem units employing advanced verification methodologies.
• Gain deep understanding of design implementation to define verification scope and develop effective verification infrastructure ensuring design correctness.
• Create detailed test plans and verification strategies for intricate IP blocks and subsystems.
• Develop reusable models such as bus functional models, monitors, checkers, and scoreboards, applying coverage-driven verification approaches.
• Implement advanced verification techniques including SystemVerilog and Universal Verification Methodology (UVM).
• Achieve functional coverage closure as part of verification completion.
• Collaborate closely with architects, designers, as well as pre- and post-silicon verification teams to fulfill project objectives.

Required Qualifications and Experience

• Bachelor's or Master’s degree in Technology or equivalent practical experience.
• Minimum of 5 years experience in verification of complex IP cores, units, and subsystems.
• Proven background in utilizing random stimulus, functional coverage, and assertion-based verification techniques.
• Strong expertise in Verilog language.
• Familiarity with SystemVerilog or comparable hardware verification languages and methodologies such as UVM or VMM.

Preferred Skills

• Experience verifying memory subsystem or network interconnect IP.
• Robust analytical and debugging capabilities complemented by proficient scripting skills.
• Excellent communicator and effective team player.

Additional Information

Our organization offers competitive remuneration and a comprehensive benefits package. We pride ourselves on being one of the world's most sought-after employers, staffed by some of the brightest minds in technology. This opportunity is ideal for candidates who are creative, independent, and thrive on challenge.

We are committed to equal employment opportunities and embrace diversity across all dimensions including race, religion, gender, age, sexual orientation, veteran status, and disability.