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Job description
Role Overview
This position involves full responsibility for digital circuit physical implementation activities, ranging from RTL to GDSII, including power and signal integrity signoff processes. The engineer will execute comprehensive static timing analysis (STA) signoffs, assist in establishing STA signoff protocols, and conduct SPICE simulations for critical timing paths to ensure design robustness.
Key Responsibilities
- Manage the flow of physical design, including placement, routing, power verification, and physical integrity signoff with the latest EDA tools and technologies.
- Optimize and maintain design methodologies and flows used for placement, routing, power verification, and STA.
- Drive the adoption of cutting-edge fabrication technologies and advanced EDA software tools.
- Engage in power-performance-area (PPA) and yield enhancement initiatives, developing necessary tools and refining design processes to improve efficiency and results.
Candidate Qualifications
- Demonstrated proficiency across the full digital physical design flow from RTL to final GDS, with hands-on experience in EDA tools such as Innovus (INVS), Fusion Compiler (FC), PrimeTime (PT), Pegasus (PX), RedHawk (RH), and Calibre.
- Strong expertise in static timing analysis methodologies and workflows is essential.
- Working knowledge of synthesis tools like Design Compiler (DC) or Fusion Compiler (FC).
- Experience with top-level placement, routing, power verification, power integrity, bump planning, or electrostatic discharge (ESD) planning is advantageous.
- Familiarity with advanced node signoff criteria is preferred.
- Proven track record of successful tape-outs involving ultra-low-voltage, large-scale, or complex IP designs is highly desirable.
- Understanding and experience with low-power design techniques and power analysis methodologies.
- Strong programming abilities using scripting and programming languages such as Tcl, Python, Perl, C, or C++.
- Knowledge of 3D integrated circuit (IC) design and relevant practical experience is a plus.
- Prior involvement in STA signoff processes for tape-out projects is beneficial.
Additional Information
This role is based in Singapore and requires onsite presence. It is a full-time employment opportunity. There is no specified number of vacancies or salary disclosed. Eligible applicants are not specifically restricted. Candidates with relevant experience and skills in digital physical design are encouraged to apply.