Analog Layout Engineer

Company Overview

Qualcomm India Private Limited is seeking an Analog Layout Engineer to join their Engineering Services Group. The role involves designing block, macro, or chip-level layouts and floorplans aligned with project specifications and design schematics.

Key Responsibilities

The engineer will apply knowledge of design manuals, standard layout processes, layout elements, and fundamental electronics to develop accurate designs fulfilling project objectives. The role entails performing analyses, testing, and verification of layouts through various tools and methodologies to detect and resolve issues. Collaboration is essential, working closely with both internal teams and external partners to ensure project alignment, provide updates, and troubleshoot challenges.

Required Qualifications and Experience

• Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related disciplines with a minimum of 2 years custom layout design experience in analog, mixed signal, RF, or digital domains.
• Alternatively, Associate's degree plus 4+ years relevant experience, or High School diploma with 6+ years related work experience.
• Hands-on proficiency of at least 2 years with layout design and verification tools such as Cadence, LVS, and RMAP.
• Advanced degrees may substitute for up to 2 years of required experience (Master’s = 1 year, Doctorate = 2 years).
• Industry experience ranging 3 to 6 years in Mixed-Signal layout design with a Bachelor’s degree in electrical or electronic engineering is typical.

Technical Skills and Domain Expertise

• Independently managing block-level analog layout design from schematics, including estimation of area, optimization of floorplan, routing, and design verification.
• Expertise designing analog blocks including amplifiers, comparators, voltage/current references, data converters, and timing circuits.
• Experience with RF blocks like LNAs, transmitters (TX), receivers (RX), synthesizers (SYNTH), and baseband filter (BBF) blocks is regarded as an advantage.
• Strong troubleshooting ability for LVS (Layout Versus Schematic) and DRC (Design Rule Check) errors, especially for advanced technology nodes at 14nm FinFET and smaller.
• In-depth understanding of critical layout considerations such as matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding techniques, parasitic effects, and short channel phenomena.
• Familiarity with EDA tools including Cadence Virtuoso Layout Editor, VXL, and Calibre RVE.

Additional Qualities

• Effective interpersonal communication skills combined with strong analytical thinking for resolving technical issues professionally.
• Accountability for delivering high-quality layouts on schedule.

Equal Opportunity and Accessibility

Qualcomm is an equal opportunity employer dedicated to an accessible recruitment process. Applicants with disabilities can request reasonable accommodations to facilitate participation in hiring procedures, by contacting the company directly. Qualcomm is committed to maintaining a workplace inclusive of individuals with disabilities.

Policy and Application Notes

Employees must adhere to company policies regarding confidentiality and security protocols. Qualcomm does not accept unsolicited resumes from staffing or recruiting agencies. Candidates should not send resumes through third-party agencies or company distribution lists, as such submissions will not be considered or compensated.