STA Design Engineer

About the Role

Join a prominent global semiconductor leader as an experienced STA Engineer, contributing to advanced static timing analysis (STA), timing constraint development, and performance optimization for high-performance, power-efficient semiconductor products. You will play a crucial role within the STA team responsible for detailed block and top-level timing evaluations to ensure excellent performance and energy efficiency in sophisticated cores and System on Chips (SoCs).

Situated at the company's R&D center in Cork, Ireland, you will collaborate cross-functionally to achieve timing closure and validate timing models, significantly impacting product delivery success.

Responsibilities

• Conduct timing signoff activities focusing on Snapdragon cores and SoC methodologies and flows, including static timing analysis and closure for complex core and full-chip SoCs.
• Improve and refine existing STA and timing closure techniques and methodologies continually.
• Enhance the accuracy of timing closure and static/dynamic flows to reduce turnaround times effectively.
• Ensure strict adherence to timing signoff checklists and criteria throughout all processes.
• Automate timing and power data mining and processing tasks to improve efficiency.
• Engage in project proposal preparation, defining key milestones and deliverables.
• Execute project goals timely while providing production support and troubleshooting throughout all development stages.
• Resolve issues proactively to maintain smooth project execution.

Candidate Profile

• Minimum of four years’ professional experience in related roles.
• In-depth knowledge and practical proficiency with STA tools such as PrimeTime, PrimeShield, or Tempus, especially for hierarchical analysis in large SoC designs.
• Hands-on experience using Tweaker, PrimeClosure, PTECO, or Tempus ECO tools for timing closure is essential.
• Advanced automation skills using scripting languages including Python, TCL, or Perl.
• Strong understanding of ASIC design flows, spanning RTL to GDS stages.
• Interest in Design for Parametric Yield provides additional advantage.
• Exposure to extraction and circuit simulation tools and environments is beneficial.
• Excellent analytical and problem-solving abilities with a results-oriented mindset suitable for a research-driven setting.
• Effective communication skills and ability to collaborate within a fast-paced, multidisciplinary engineering team.

Additional Information

Applicants acknowledge that personal data provided in connection with this opportunity will be collected, stored, and processed as per the company's privacy policies at their designated R&D Center in Cork, Ireland.