Lead Functional Formal Verification Engineer

Role Overview

We are looking for a skilled Lead Functional Formal Verification Engineer to spearhead the formal verification activities for intricate digital design projects. This role emphasizes ensuring the integrity and dependability of sophisticated digital IP, SubSystems, or SoCs through advanced verification techniques.

Key Responsibilities

• Take full ownership of formal verification efforts for one or multiple design blocks and IPs, developing robust verification strategies and detailed test plans.
• Design and implement comprehensive formal verification test plans and precise specifications to guarantee exhaustive validation of design features.
• Demonstrate design properties and detect design bugs; work closely with design engineers to refine micro-architectural elements and verify design precision.
• Innovate verification methodologies by creating reusable and performance-optimized formal models and code bases tailored for complex architectures.
• Provide mentorship and technical guidance to junior engineers, championing best practices in formal verification methods and industry toolsets.
• Coordinate with cross-discipline teams such as design and verification to ensure proper integration of formal verification into overall verification workflows.

Candidate Profile and Required Qualifications

• A Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or equivalent specialization.
• Minimum of 5 years' experience conducting formal verification for complex IPs, SubSystems, or SoCs, with a solid grounding in digital logic design and verification strategies.
• Proficiency in formal verification tools and property specification languages such as SVA and PSL, along with expertise in hardware description languages including SystemVerilog, Verilog, or VHDL.
• Hands-on experience with standard industry EDA formal verification tools.
• Familiarity with scripting languages like Python, Tcl, Perl and programming capabilities in C, C++, or SystemC.
• Strong analytical and problem-solving skills to troubleshoot intricate technical challenges and enhance verification efficiency.
• Excellent communication skills and ability to collaborate effectively within multi-disciplinary teams.
• Proven leadership skills demonstrated through mentoring junior personnel and advancing formal verification methodologies.

Preferred Expertise

• Experience with complex digital architectures such as CPUs or GPUs, with knowledge of relevant protocols like AXI, CHI, and PCIe.
• Understanding of UVM and other simulation-based verification techniques.
• Familiarity with advanced formal verification performance optimization methods including abstraction, property decomposition, and state-space reduction.
• Expertise using Jasper or VC Formal verification tools is highly advantageous.

Location

This position is based in Bengaluru, Karnataka, India, requiring onsite presence.