Analog Layout Engineer

Role Overview

LeadSoc Technologies Pvt Ltd is seeking a seasoned Analog Layout Engineer with over 4 years of experience skilled in developing precise custom and analog layouts for cutting-edge lower-node semiconductor technologies such as FinFET processes. The engineer will be crucial in delivering robust, high-performance physical layouts aligning with design and foundry specifications.

Key Responsibilities

• Develop custom analog and mixed-signal physical layouts for various semiconductor IPs and blocks.
• Work extensively with lower-node and advanced technology nodes, including FinFET and similar.
• Convert circuit schematics and design objectives into optimized layout implementations.
• Perform comprehensive layout design, optimization, and physical verification processes.
• Conduct physical verification steps including DRC (Design Rule Check), LVS (Layout Versus Schematic), ERC (Electrical Rule Check), and effectively resolve related violations.
• Collaborate closely with Analog Design, Circuit Design, Physical Verification, and Technology teams to ensure layout integrity and quality.
• Analyze layout issues and enhance layout performance parameters such as area, matching accuracy, and parasitic effects.
• Execute post-layout verification and debugging activities.
• Ensure compliance with foundry-imposed design rules and manufacturing technology requirements.
• Contribute to design reviews, tape-out preparations, and meeting project milestones.
• Maintain thorough documentation and adhere strictly to established layout methodologies and quality processes.

Required Skills and Experience

• A minimum of 4 years’ experience in Analog or Custom Layout Design.
• Proficient with analog layout techniques and physical design principles.
• Hands-on experience with lower-node advanced semiconductor technologies.
• Strong expertise in physical verification tools and processes including DRC, LVS, ERC.
• Solid understanding of analog matching techniques and layout fundamentals.
• Experience using Cadence Virtuoso or equivalent custom layout software.
• Good knowledge of CMOS device physics, parasitic effects, and layout-dependent phenomena.
• Ability to handle complex analog circuit layouts and address layout-related challenges.
• Capable of working autonomously and collaboratively with cross-functional teams.

Preferred Experience

• Layout experience with any of these advanced analog blocks: PLL/DLL, ADC/DAC, Bandgap/reference circuits, LDO/power management modules, amplifiers, comparators, SerDes/high-speed interfaces, data converters, mixed-signal IPs, or memory-associated analog components.

Additional Information

Candidates should be available to commence work immediately or within a 15-day notice period. The role is based in Bangalore or Hyderabad, India. Detailed CV submissions are expected.