High Level Synthesis Compiler Engineer

Role Overview

Join Altera as a High Level Synthesis Compiler Engineer, focusing on developing and enhancing our compiler and software tools that convert RTL and constraints into achievable FPGA designs. This role involves advancing lowering, optimization, and integrating these components within the larger implementation, timing, and debug processes. You'll create dependable, scalable tools, mentor engineers, and engage closely with customers to ensure their complex design requirements remain feasible and practical within our toolset.

Key Responsibilities

• Advance and refine the compiler for the FPGA design workflow, including IR and lowering processes, analysis and transformation phases, and optimizations focused on correctness and quality of results, ensuring scalability for runtime and memory on extensive designs.
• Collaborate with customers to grasp their applications, workflows, and success measures; represent their needs regarding capabilities, quality, and speed by driving specific compiler and flow enhancements proactively.
• Provide mentorship to engineers through code and design reviews, technical coaching, fostering ownership, sound design decisions, and high execution standards within the team.
• Create clear documentation detailing behaviors, limitations, and workarounds for both internal team members and external stakeholders as needed.
• Maintain up-to-date knowledge of EDA and compiler technologies, including LLVM and MLIR ecosystems where relevant, as well as FPGA design methodologies and applicable standards.

Required Qualifications

• A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field.
• At least eight years of professional experience developing compilers, LLVM/MLIR tools, or EDA/FPGA implementation software.
• Proficient in C++ applied to production systems emphasizing performance, multi-threading, and managing sizeable codebases.
• Practical experience with MLIR and/or LLVM, including IR architecture, passes, backends, or integration within broader compiler or EDA workflows.
• Strong background in digital design and FPGA fundamentals, including LUT/FF/BRAM/DSP primitives, clocking, timing, and impacts on quality of results by tool selections.
• Familiarity with FPGA or ASIC implementation stages such as synthesis, place-and-route, static timing analysis, and constraints, understanding potential design failures.
• Excellent communication and teamwork skills for effective customer interaction and translating objectives into actionable engineering tasks.
• A mentorship-oriented approach demonstrated by successes in guiding engineers via reviews, paired work, and technical support.

Preferred Qualifications

• PhD in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.
• Experience with simulation, formal verification, debugging environments, or high-level design flows like HLS and their integration with back-end systems.
• A background in delivering software utilized by external clients or significant internal user bases.

Compensation and Employment Details

The salary range is approximately 124100 to 179700 CAD annually, reflecting the Canadian labor market and adjusted based on location, expertise, skills, training, and job-specific experience. Performance-incentive bonuses recognizing individual and company achievements complement the base pay.

This position uses artificial intelligence to assist with candidate screening and applies to existing openings. Canadian work experience is not mandatory. Employment type is full-time on-site in Toronto, Ontario, Canada.

Equal Opportunity Statement

Altera is committed to an inclusive workplace and will provide employment consideration without discrimination based on race, color, religion, sex, national origin, age, disability, veteran status, gender identity or expression, sexual orientation, or any other protected characteristic under applicable laws.