Analog Layout Engineer

About the Role

We seek a skilled Analog Layout Engineer with 4 to 10 years of experience to support our semiconductor design team focusing on high-performance analog and mixed-signal IPs using advanced CMOS/FinFET technologies. The candidate will develop full-custom layouts for complex integrated circuits, primarily using TSMC technology nodes.

Key Responsibilities

• Create full-custom analog and mixed-signal IC layouts for challenging designs.
• Design layouts for analog building blocks including operational amplifiers, bandgap references, low-dropout regulators, ADC/DAC modules, PLL/DLL circuits, charge pumps, current and voltage references, and high-speed I/O along with SerDes/DDR PHY circuits.
• Apply advanced layout techniques such as common-centroid placement, interdigitation, symmetry, device matching, dummy devices, guard rings, shielding, and isolation of sensitive nodes.
• Optimize layouts by accounting for parasitics to minimize routing and device parasitic impact on circuit performance.
• Collaborate closely with analog circuit designers to transform schematics into optimized and verified physical layouts.
• Execute design rule, layout vs schematic, electrical rule checks, and other physical verifications, resolving layout-related issues.
• Support parasitic extraction and post-layout simulation to refine the layouts accordingly.
• Ensure layouts satisfy area, matching, noise, reliability, electromigration/IR drop, and performance criteria.
• Work extensively with advanced TSMC CMOS and FinFET technology nodes, including 16nm and below.
• Coordinate with design, verification, reliability, and physical implementation teams through the full design cycle.
• Assist in IP integration, top-level layout tasks, tapeout preparations, and proper documentation.
• Participate actively in design reviews and contribute to the enhancement of layout methodologies and productivity.

Required Qualifications and Experience

• Bachelor's or Master's degree in Electrical/Electronics Engineering, VLSI, or related disciplines.
• Between 4 and 10 years of practical experience in analog/mixed-signal IC layout.
• Proven ability with full-custom analog layout techniques, particularly on TSMC technology nodes.
• Experience preferred on advanced technology nodes at 16nm or smaller feature sizes.
• Deep understanding of analog layout principles including device matching, parasitic effects, routing, noise isolation, and reliability.
• Familiarity with physical verification tools and methodologies like DRC, LVS, ERC.
• Hands-on experience with parasitic extraction and post-layout simulation/debugging.
• Competent in independently managing the entire flow from schematic to tapeout for analog blocks.

Preferred Tools and Technologies

• Cadence Virtuoso and Cadence Layout XL for layout design
• Calibre and PVS or Assura for physical verification
• StarRC, Quantus or similar parasitic extraction tools
• TSMC CMOS and FinFET nodes including 16nm, 12nm, 7nm, 5nm, and newer

Additional Preferred Experience

• Familiarity with layouts for SerDes PHY, DDR/LPDDR PHY, high-speed I/O
• Experience designing PLL, DLL, CDR, ADC, DAC, power management ICs, data converters, and precision analog blocks
• Exposure to high-speed analog/mixed-signal circuit layouts

Key Competencies

• Strong fundamentals in analog layout methodology
• Expertise in device matching and parasitic-aware design
• Experience with advanced process nodes
• Competence in physical verification and debugging
• Sound understanding of schematic to layout flow
• Ability to work autonomously and collaborate across teams
• Experience in tapeout processes