Staff Engineer - Static Timing Analysis (STA)

About the Role

We are seeking a seasoned Static Timing Analysis (STA) Engineer to join our team in Bengaluru or Hyderabad. This pivotal position requires deep expertise in timing sign-off processes for complex System on Chip (SoC) designs. The ideal candidate will possess hands-on experience in timing closure, development of timing constraints, and collaboration with Physical Design and RTL teams to ensure design completion.

Primary Responsibilities

• Conduct block-level and full-chip static timing analysis on intricate SoC projects.
• Develop and rigorously validate timing constraints using Synopsys Design Constraints (SDC) files.
• Lead timing closure initiatives across various operational corners and modes.
• Analyze and troubleshoot setup and hold timing violations effectively.
• Collaborate closely with Physical Design, RTL, and Architecture teams for design synchronization.
• Support Engineering Change Order (ECO) implementations aimed at timing rectifications.
• Manage timing sign-off activities required for tape-out procedures.
• Perform detailed clock tree and timing path assessments.

Mandatory Skills and Expertise

• Extensive knowledge and experience with Static Timing Analysis methodologies.
• Proficiency in Synopsys PrimeTime for timing verification and sign-off.
• Strong grasp of timing constraint formulation with SDC files.
• Demonstrated success in achieving timing closure and sign-off on complex designs.
• Understanding of clocking architectures and clock domain crossing (CDC) concepts.
• Exposure to cutting-edge technology nodes relevant to physical design.
• Solid understanding of the physical design flow process.

Additional Beneficial Experience

• Background in CPU, GPU, or high-performance SoC design environments.
• Familiarity with low power design methodologies such as UPF and CPF.
• Experience with synthesis and physical design workflows.
• Knowledge of ECO implementation and sign-off processes.

Experience and Work Style

• Minimum of 10 years specializing in STA and timing analysis fields.
• Strong analytical skills for debugging and resolving timing issues.
• Capability to work autonomously and drive critical timing closure efforts.

Additional Information

Preferred notice period for candidates ranges from immediate availability up to 30 days.