Analog Layout Engineer

Role Overview

This position involves the design and development of critical analog and mixed-signal circuits, alongside full-chip integration support. The engineer will be responsible for thorough layout verification processes including LVS, DRC, and Antenna checks, ensuring quality compliance and proper documentation. Timely delivery of block-level layouts with high standards of quality is critical.

Key Responsibilities

• Plan and execute layout design activities for analog and mixed-signal blocks with attention to area and timing estimations, project scheduling, and effective delegation across multiple projects.
• Mentor junior engineers by guiding them on sub-block level layouts and reviewing their contributions.
• Interface directly with clients to maintain quality assurance, resolve technical issues, and ensure customer satisfaction.
• Comprehend project requirements, conduct design reviews, validate architectures, and uphold excellent service standards in technology delivery.
• Participate actively in project estimation, solution delivery input, risk management, code and unit test plan reviews to maintain best practices.
• Lead teams in crafting optimized, high-quality design outputs while promoting continual knowledge enhancement and compliance with organizational protocols.
• Contribute significantly to constructing efficient programs and systems facilitating clients’ digital transformation journeys.

Essential Skills & Experience

• Minimum of 3 years experience in analog/custom layout design within advanced CMOS technologies.
• Proficient expertise with Cadence Virtuoso L/VXL and Calibre DRC/LVS tools is mandatory.
• Experience with SKILL or Perl scripting is considered advantageous.
• Hands-on experience designing critical analog blocks such as temperature sensors, PLLs, ADCs, DACs, LDOs, bandgap references, charge pumps, current mirrors, comparators, and differential amplifiers.
• Thorough understanding of analog layout principles, including matching, electro-migration, latch-up, coupling, cross-talk, IR drop, and management of active and passive parasitic effects.
• Knowledge of how layout influences circuit parameters like speed, capacitance, power consumption, and area.
• Capability to interpret design constraints to produce layouts meeting stringent quality standards.
• Strong written and verbal communication skills for effective collaboration and documentation.