Analog Layout Engineer

Job Responsibilities

• Design custom layouts for high-speed analog and digital blocks including ring oscillators, dividers, bias blocks such as voltage and current references, and pre-drivers using TSMC 3nm technology and below.
• Independently debug and resolve layout issues identified during verification processes.
• Adapt to various project-related tasks as required.
• Assume full ownership and responsibility for assigned blocks and complex macros.
• Manage release processes, ensuring timely completion of milestones, and proactively raise concerns regarding any expected challenges.
• Collaborate closely with the team for block-level specifications to enhance top module integration.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering (B.Tech/B.E./M.S./M.E./M.Tech).

Essential Skills

• More than 10 years of comprehensive experience in independently handling block/module layouts utilizing Cadence layout design tools.
• Mandatory experience with TSMC 5nm process node or smaller technologies.
• Proficient with layout design and verification software including Cadence Virtuoso EXL/GXL and Calibre.

Preferred Skills

• Demonstrated leadership in module and macro-level layout projects with effective communication for coordination among team members during layout integration.
• Familiarity with scripting languages such as SHELL, PERL, SKILL and proficiency in Excel is advantageous.