STA/Timing Methodology Engineer (Lead/Staff)

About the Company

Qualcomm is a pioneer in technology innovation, pushing the limits to enable future-ready experiences and advancing digital transformation towards a smarter connected world. As a Hardware Engineer at Qualcomm, you will engage in the design, optimization, verification, testing, and yield enhancement of electronic and mechanical systems, digital, analog, RF, optical components, as well as test and packaging systems to support world-class product launches. Collaboration across cross-functional teams is key to developing solutions that meet stringent performance criteria.

Role Summary

This position calls for an experienced STA and Timing Methodology Engineer with extensive hands-on expertise in timing sign-off and convergence on complex System-on-Chip (SoC) designs, with 6 to 10 years of experience. The candidate should be ready to commence immediately, working closely with Physical Design and Methodology teams across multiple locations and technology nodes.

Key Responsibilities

• Establishing and managing STA setup, convergence, review, and timing signoff for designs involving multiple modes and voltage domains.
• Performing timing analysis, validation, and debugging across diverse process, voltage, and temperature (PVT) corners using Primetime and Tempus tools.
• Optimizing STA flows and correlating spice simulation results with STA analysis.
• Assessing various timing methodologies and tools across different projects and technologies.
• Developing automation scripts within STA and Physical Design tools to enhance methodologies.
• Collaborating effectively within cross-disciplinary teams.
• Working with digital design implementation flows including RTL to GDS stages using tools like ICC, Innovus, and Primetime or Tempus.
• Supporting process technology enablement through circuit simulations using Hspice, FineSim, and Monte Carlo techniques.

Qualifications & Experience

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related fields with minimum 2 years hardware engineering experience; or Master's degree with 1+ year experience; or a PhD in relevant disciplines.
• Strong proficiency in STA timing analysis fundamentals including AOCV/POCV, CTS, latch transparency, zero/multi-cycle path management.
• Proven expertise with STA tools such as PrimeTime and Tempus.
• Experience managing timing convergence at SoC and hard macro levels.
• Knowledge of crosstalk noise mitigation, signal integrity, layout parasitic extraction, and feed-through handling.
• Familiarity with ASIC back-end design flows and tools such as ICC2 and Innovus.
• Hands-on experience with spice circuit simulation tools like Hspice and FineSim and Monte Carlo analysis.
• Skillful in scripting languages including TCL, Perl, and Python.
• Basic understanding of device physics concepts.

Additional Information

Qualcomm is an equal opportunity employer committed to providing accessible hiring processes and workplaces for individuals with disabilities. Applicants requiring accommodations during the application or hiring process can contact Qualcomm's dedicated support email. Note that this contact is for accommodation needs only and not for application status inquiries.

Employees at Qualcomm are required to comply with company policies related to security and confidentiality.

Recruitment agencies are not authorized to submit resumes or applications; unsolicited submissions will not be considered or compensated.